List of Published Papers [Google Scholar Profile]
International Conference Papers (Download Papers)
- Reversible Programmable Logic Arrays (2016)
- Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis (2015)
- On the Analysis of Reversible Booth’s Multiplier (2015)
- Minimum cost fault tolerant adder circuits in reversible logic synthesis (2012)
- Efficient approach to design low power reversible logic blocks for Field Programmable Gate Arrays (2011)
- An efficient approach for designing and minimizing reversible programmable logic arrays (2012)
- Efficient Design of Check Circuit to detect Multiple Cell Errors in Reversible Logic Synthesis (2011)
- Efficient Approach to design Reversible Fault Tolerant Cyclic Redundancy Check Circuit (2011)
- Online Testable Fault Tolerant Full Adder in Reversible Logic Synthesis (2011)
Journal Paper
- Online Testable Fault Tolerant Full Adder in Reversible Logic Synthesis (Extended Version) (2012).
Ongoing Research
- Novel Approach to design Reversible Programmable Logic Arrays.
- Reversible Decoder, Reversible Sub-tractor, Reversible Multiplexer.
Learning Materials on Reversible Computing [Presentation]
Fault Tolerant and Online Testability.ppt | |
File Size: | 2596 kb |
File Type: | ppt |
Quantum Cost Calculation of Reversible Circuit.ppt | |
File Size: | 3389 kb |
File Type: | ppt |
Reversible PLAs Simulation Tools and Corresponding Tutorials [Resources]
Benchmark PLAs.zip | |
File Size: | 44 kb |
File Type: | zip |
Presentation on Benchmark Functions Analysis.ppt | |
File Size: | 287 kb |
File Type: | ppt |
Reversible PLAs.pdf | |
File Size: | 473 kb |
File Type: |
Benchmark Circuit [SOP Format].zip | |
File Size: | 206 kb |
File Type: | zip |